Computing systems have made significant contributions toward the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous devices, such as desktop personal computers (PCs), laptop PCs, tablet PCs, netbooks, smart phones, servers, and the like have facilitated increased productivity and reduced costs in communicating and analyzing data in most areas of entertainment, education, business, and science. One common aspect of computing systems is computing device readable media, commonly referred to as memory.
Data and instructions used by the computing system can be stored in and retrieved from one or more memory devices. When reading or writing to memory a corresponding read or write voltage potential is applied to a given word line based upon a decoded memory address. Referring to FIG. 1, a block diagram of a word line decoder and driver path architecture, according to the conventional art, is shown. The word line decoder and driver path 100 can include a plurality of flip flops 110 configured to latch a received address 120 upon receipt of a clock signal (e.g., rising or falling edge of a system clock signal) 130. A set of address buffers 140 can be configured to buffer the latched address bits from the flip flops 110. A word line pre-decoder 150 can be configured to partially decode the address in the address buffer 140. In one implementation, the word line pre-decoder 150 can be configured to decode a block, bank and/or the like portion of the memory from the address. A word line decoder 160 can be configured to decode a given word line from the partially decoded address from the word line pre-decoder 150. A level shifter 170 can be configured to shift the relatively low voltage potential signal propagating through the flip flops 110, address buffer 140, word line pre-decoder 150 and word line decoder 160 to an appropriate high voltage potential signal. A high voltage driver 180 can drive the word line 190 with the appropriate high voltage potential signal from the level shifter 170 during a read, write or erase operation. The combination of the flip flops 110, address buffers 140, word line pre-decoder 150 and word line decoder 160 can comprise an address decoder circuit, and the combination of the level shifter 170 and high voltage driver 180 can comprise a word line driver circuit.
The propagation delay through the word line decoder and driver path can be the sum of the clock-data out set up time of the flip flops 110 TC→Q, the propagation delay in the address buffers 140 TAB, the propagation delay through the word line pre-decoder 150 TWPD, the propagation delay through the word line decoder 160 TWD, and the propagation delay through the level shifter 170 and high voltage driver 180 TWDR. However, as computing devices continue to evolve there is a continuing need for faster memory devices. One possible way to increase the speed of the memory device is to reduce the propagation delay through the word line decoder and driver path. Therefore, there is a need for an improved word line decoder and driver path architecture.